Such a pair of processors (which may also be termed computers) is known per se, for example, from U.S. Pat. Nos. 4,030,074, and 3,786,433. Reference in this connection may further be made to my copending application Ser. No. 452,202 filed on Dec. 22, 1982, now U.S. Pat. No. 4,654,784, according to which two interconnected support processors alternatively control a plurality of switching modules each including a pair of central processing units or CPUs likewise mated in a master-slave relationship.
In many instances, such a processor includes--besides its CPU--two distinct types of memory, namely a so-called mass memory of the nonvolatile kind and an entirely electronic, usually volatile working memory for the temporary storage of data and instructions to be used in controlling the operation of associated peripheral units. When the processor designated as the master malfunctions, that role is assigned to its twin while diagnostic operations are being carried out to trace and correct the defect. After corrections have been made, the erstwhile master is relegated to the role of standby or slave in order to be available if the current master should fail. For this purpose it is, of course, necessary that the contents of the mass memory of the newly designated slave processor be updated so that its contents are identical with those of the other mass memory in order that the two component can operate in synchronism. Though the contents of the originating mass memory are left intact, thanks to their nondestructive readout this procedure will be referred to hereinafter as a transfer.
When the slave processor has been out of service for an extended period, the transfer of a large number of data words--e.g. several tens of megabytes--from the mass memory of the master by conventional means may be quite time-consuming and can possibly last for several hours during which the operation of the master processor is inhibited. The transfer time could be shortened by the technique of direct memory access (DMA) which, however, cannot be utilized for direct communication between the two mass memories on account of synchronization problems. Thus, prior-art DMA data transfers between the mass memories of mated processors had to proceed through three distinct phases, namely a first phase of transfer from the mass memory of the master processor to its own working memory, a second phase of transfer from the working memory of this processor so that of its twin, and a third phase of transfer from the latter memory to the mass memory of the slave processor. With the first two transfers occurring under the control of the master CPU, its operating program had to undergo a prolonged interruption.
Such program interruptions are, of course, acceptable for short intervals, as where only a few data words are to be transferred from time to time in the course of normal operations. There are also instances in which data words are to be transferred directly from the working memory, rather than from the mass memory, of the master processor to that of its twin.